Nanotech 2013 Vol. 2
Nanotech 2013 Vol. 2
Nanotechnology 2013: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational (Volume 2)

Modeling & Simulation of Microsystems Chapter 7

Numerical Study on Gate-All-Around Tunneling FET with SiO2 Core and Si Shell Structure

Authors: X. Zhang, A. Zhang, J. Mei, L. Zhang, H. He, J. He, M. Chan

Affilation: PKU-HKUST Shenzhen-Hongkong Institution, China

Pages: 512 - 515

Keywords: nanowire, core-shell, tunnling field-effect transistor (TFET), band-to-band tunneling, quantum confinement effect

This work presents a gate-all-around tunneling FET based on SiO2 core and Si shell structure (GAA-SOI-TFET) and demonstrates its performance characteristics via the numerical simulation method. The 3-D T-CAD numerical simulations demonstrate that this new device has steep subthreshold swing (<60mV/dec), suppressed drain-induced barrier lowering, and enhanced Ion/Ioff ratio up to 109 orders of magnitude. It is worth noting that Ion begins to increase when SiO2 core radius exceeds a specified value (~4nm) while influence of gate oxide thickness on the device performance being an important factor.

ISBN: 978-1-4822-0584-8
Pages: 808
Hardcopy: $209.95