Authors: B. Karunamurthy, T. Ostermann and M. Bhattacharya
Affilation: KAI Kompetenzzentrum Automobil- und Industrieelektronik GmbH, Austria
Pages: 489 - 492
Keywords: simulation, thermo-mechanics, reliability, chip-package, virtual fabrication
A methodology for simulating the accurate structural details of a non-planarized technology chips is presented. This approach uses a virtual semiconductor fabrication technique to create geometry and finite element mesh on complex chip topology features. Thermo-mechanical related failures account for 65% of the reliability problems in the semiconductor industry. These failures, such as cracks and delamination are driven by stress arising due to the thermal coefficient mismatch between the chip and package materials. Multi-scale simulations on a chip-package system are required in order to evaluate the stress induced on the chip by the package when exposed to thermal loads. Accurate chip topology features must be included to predict the stress behavior and singularities. The first part of this paper describes the techniques used to generate the 3D geometry by utilizing voxel modelling engine. This also covers the mesher function to generate surface and volume mesh, which can be exported to a FEM solver. The modelling methodology for multi-scale simulations is presented in the next part, along with the description of material models used. Finally, results obtained with this methodology on a power metallization stack of a power IC are presented.
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