Authors: G.C. Patil, S. Qureshi
Affilation: Indian Institute of Technology Kanpur, India
Pages: 44 - 47
Keywords: Schottky barrier, variability, CMOS, nanoscale
Recently, metal source/drain (S/D) dopant-segregated Schottky barrier (DSSB) SOI MOSFET has attracted the attention of researchers due to its planar structure, CMOS compatibility and reduced S/D series resistance at thin SOI film. However, employing dopant-segregation during silicidation leads to an increase in the process induced device parameter variations and the inhomogeneity in SB height (Φbn) increases the threshold voltage variability of the device. To alleviate this problem, we have shown that, employing partial buried oxide only under the metal S/D and p-type δ-doping under the epitaxial channel of DSSB SOI MOSFET suppresses the variability induced by process fluctuations in dopant segregation length (LDSL), Φbn and SOI film thickness (TSi) of the device. In addition, for the first time, the impact of variability on digital/analog circuit performance metrics such as leakage power dissipation (IOFF.VDD), intrinsic gate delay (CG.VDD/ION), cut-off frequency (ft) and open-circuit voltage gain (AVopen) of this device has been investigated. The results show that, although in comparison to DSSB SOI MOSFET the standard deviation (σ) in AVopen of proposed device is larger, the significant reduction in σ(IOFF.VDD), σ(CG.VDD/ION) and σft shows the suitability of the proposed device for low-variability nanoscale digital/analog circuits.
Nanotech Conference Proceedings are now published in the TechConnect Briefs