Authors: J.J. Seliskar
Affilation: HiperSem Inc., United States
Pages: 582 - 585
Keywords: CMOS, Nanosystem, I/O, Interconnect, PHY Layer, Analog, Mixed-Signal
Analysis of the constant-voltage scaling characteristics of Fully-Depleted Castellated Gate (FDCG) MOSFETs reveals near term opportunities for these devices as the replacement for the “thick oxide” I/O device in CMOS System-On-A-Chip (SoC) technologies (e.g. the power transistor). Looking forward to the era of post-CMOS Integrated Nanosystems, FDCG MOSFETs utilized as PHY layer devices may provide the essential interoperable infrastructure for existing and yet-to-be-defined nanoscale devices.
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