Authors: T. Nakagawa, T. Sekigawa, T. Tsutsumi, Y. Liu, M. Hioki, S. O’uchi, H. Koike
Affilation: Electroinformatics Group, Japan
Pages: 861 - 864
Keywords: compact model, MOSFET, double-gate
We have proposed a compact model for four-terminal double-gate MOSFETs based on double charge-sheet model. The model can handle asymmetric gate structure such as different gate-oxide thickness, as well as independent gate voltage for two gates. The transport equation accommodates carrier velocity saturation explicitly. This approach guarantees, though approximated it is, physics based carrier profile calculation, in sharp contrast to conventional approaches where, at large drain voltage, very small carrier density near the drain results. Comparison with 2D device simulator shows that accurate intrinsic capacitance model has been obtained only by the analytical derivative of channel carrier with respect to the terminal voltage. The model was compared with the experimental data. The reference samples were fabricated by using lightly doped p-type (110) SOI wafers. The silicon channel was formed by wet etching to obtain flat interfaces. The interface plane was oriented to (111), which was necessary for preferential etching. Comparison between the model and the experimental data shows that the model is in good agreement except near-threshold condition, where relatively high drain current is obtained in the model. Since the transport equation is accurate in the region, parasitic effects will cause the discrepancy.