Authors: S. Suryagandh, N. Subba, V. Wason, P. Chiney, Z-Y Wu, B.Q. Chen, S. Krishnan, M. Rathor, A. Icel
Affilation: Advanced Micro Devices, United States
Pages: 822 - 824
Keywords: SOI, Variation, Analog
Analog design uses transistors with longer channel length for high performance. gm, Rout and intrinsic gain form the matrix to gauge this performance. It is critical to design these circuits for manufacturing variability. This work presents a systematic compact modeling approach to capture analog variation. We show that the variation in Rout is very well correlated to the variation in DIBL, especially if the transistors are biased at around 100-200mV gate-overdrive. We observe that this correlation becomes stronger as the channel length increases. We propose a sub-circuit based approach to model DIBL variation in the corner models. This method provides accurate variability estimates of gm, Rout in the compact models for 65nm and 45nm technologies.
Nanotech Conference Proceedings are now published in the TechConnect Briefs