Papers:
Capacitance modeling of Short-Channel DG and GAA MOSFETs
Based on our framework model of the electrostatics and the drain current in short-channel, nanoscale DG and GAA MOSFETs, we here present a corresponding model for the device capacitances covering all regimes of operation from [...]
New Properties and New Challenges in MOS Compact Modeling
Zhou X., See G.H., Zhu G., Zhu Z., Zhu G., Zhu Z., Lin S., Wei C., Srinivas A., Zhang J., Nanyang Technological University, SG
As bulk-MOS technology is approaching its fundamental limit, non-classical devices such as multiple-gate (MG) and silicon-nanowire (SiNW) transistors emerge as promising candidates for future generation device building blocks. This trend poses new challenges in developing [...]
Unified Regional Surface Potential for Modeling Common-Gate Symmetric/Asymmetric Double-Gate MOSFETs with Quantum-Mechanical Effects
See G.H., Zhou X., Zhu G., Zhu Z., Zhu G., Zhu Z., Lin S., Wei C., Zhang J., Srinivas A., Nanyang Technological University, SG
The quantum mechanical effect (QME) in nanoscale MOSFETs has become more and more important. The quantization of the space charge density in bulk-MOS compact models is usually modeled by the van Dort model with a [...]
Quasi-2D Surface-Potential Solution to Three-Terminal Undoped Symmetric Double-Gate Schottky-Barrier MOSFETs
Zhu G., Zhu Z., See G.H., Zhou X., Zhu G., Zhu Z., Lin S., Wei C., Zhang J., Srinivas A., Nanyang Technological University, SG
The quasi-2D method has been used to account for short-channel effects in PN-junction MOSFETs. Recently some authors applied the quasi-2D solution to SB MOSFETs to derive potential profiles. In this paper, an improved quasi-2D solution [...]
Construction of a Compact Modeling Platform and Its Application to the Development of Multi-Gate MOSFET Models for Circuit Simulation
Miura-Mattausch M., Chan M., He J., Koike H., Mattausch H.J., Miura-Mattausch M., Nakagawa T., Park Y.J., Tsutsumi T., Yu Z., Hiroshima University, JP
We are reporting the construction of a common platform for compact model development based on the Verilog-A language and in particular a framework for efficient development of multi-gate MOSFET models for circuit simulation. Phenomena expected [...]
Unified Regional Surface Potential for Modeling Common-Gate Symmetric/Asymmetric Double-Gate MOSFETs with Any Body Doping
See G.H., Zhou X., Zhu G., Zhu Z., Zhu G., Zhu Z., Lin S., Wei C., Zhang J., Srinivas A., Nanyang Technological University, SG
Double-gate MOSFET is one of the key potential devices to allow further extension of CMOS technology scaling. The compact modeling community faces great challenges to model the physical effects due to the coupling of the [...]
Modeling of Floating-Body Devices Based on Complete Potential Description
Sadachika N., Murakami T., Ando M., Ishimura K., Ohyama K., Miyake M., Mattausch H.J., Miura-Mattausch M., Miura-Mattausch M., Hiroshima University, JP
Advanced MOSFETs exploit the carrier confinement to suppress the short-channel effect, which is realized by reducing the bulk layer thickness. The ongoing developments of the multi-gate MOSFET as well as the fully-depleted SOI-MOSFET with ultra [...]
The Driftless Electromigration Theory (Diffusion-Generation-Recombination-Trapping)
Electromigration (EM) is the transport of atoms and ions in metals at high electrical current density (>100kA/cm^2) leaving behind voids. It was delineated in 1961 by Huntington [1] in gold wire, and empirically modeled by [...]
Adaptable Simulator-independent HiSIM2.4 Extractor
This paper presents a method and its software implementation to extract Spice parameters of the HiSIM2.4 model. The completed flow of dedicated parameter extraction procedures is currently designed for the HiSIM2.4 model and can be [...]
Recent Advancements on ADMS Development
Last a few years have witnessed a quick rise of Verilog-A language as a new standard for compact model development. Consequently there are significant interests in developing softwares which compiles compact models defined in Verilog-A [...]
Source/Drain Junction Partition in MOS Snapback Modeling for ESD Simulation
A new enhancement on modeling ‘snapback’ in MOS transistors for ESD simulation is presented. The model uses standard industry models only and intrinsically includes all major physical effects in snapback. An ESD snapback MOS model [...]
Improved layout dependent modeling of the base resistance in advanced HBTs
Existing equations for describing the layout dependent base resistance are improved and extended for heterojunction bipolar transistors (HBTs) in advanced process technologies. The new equations have been developed using quasi-3D device simulation and have been [...]
The Bipolar Field-Effect Transistor Theory (A. Summary of Recent Progresses)
Field effect transistor (FET) was conceived 80 years ago in Lilienfeld ‘s 1926 1932 patents [1]. Shockley 1952 [2] invented the volume channel FET 55 years ago using two opposing p/n junctions as gates on [...]
The Bipolar Field-Effect Transistor Theory (B. Latest Advances)
Latest advances are presented on theoretical device and circuit characterizations of the Bipolar Field effect transistor (BiFET) [1]. The 2 Dimensional (2 D) rectangular geometry of the transistor (uniform in the width direction) is employed [...]
An Accurate and Versatile ED- and LD-MOS Model for High-Voltage CMOS IC Spice Simulation
The paper presents a high-voltage compact MOSFET model that has been proven physically accurate and numerically robust for various and generations of high-voltage ED (extended drain) and LD (laterally double diffused) production CMOS process technologies. [...]
Compact Modeling of Noise in non-uniform channel MOSFET
Compact MOSFET noise models are mostly based on the Klaassen-Prins (KP) method. However, the noise properties of lateral nonuniform MOSFETs are considerably different from the prediction obtained with the conventional KP based methods which, at [...]
An Iterative Approach to Characterize Various Advanced Non-Uniformly Doped Channel Profiles
Since past three decades, in the pursuit of superior performances relative to high-speed circuits and packing density, miniaturization of device dimensions has been adopted as a powerful tool. Gradually, as device feature sizes move into [...]