Mats I., Tarcenco V.
Select Techno-Fix Ltd, CA
Keywords: bonding, capacitance, JFET, packaging
The technical solutions for the Integrated Circuits (ICs) packaging remains enough conservative during microelectronics development. The ICs with active components having size of micrometers or even nanometers continue to have bonding pads area within hundreds square micrometers. The leads from the contact pads on a silicon substrate to the terminals in its package are bonded creating a parasitic capacitor. This process is one of the most critical steps that influence the reliability of the High Frequency (HF) Junction Field Effect Transistors (JFETs). We developed a bonding pad design, with parasitic capacity determined by contacting spot between the wire and bonding pad metallizing only. The proposed solution allows decreasing the gate-draining capacity in the pair of JFETs from 1.15 – 1.2 pF to 1.0 – 1.05 pF. We have supplied JFETs having bonding pads, with this technique, for wideband (0-500) MHz oscilloscopes
Journal: TechConnect Briefs
Volume: 3, Technical Proceedings of the 2007 NSTI Nanotechnology Conference and Trade Show, Volume 3
Published: May 20, 2007
Pages: 233 - 236
Industry sector: Sensors, MEMS, Electronics
Topic: Sensors - Chemical, Physical & Bio
ISBN: 1-4200-6184-4