Bauer T.
Silex Microsystems, SE
Keywords: 3d interconnect, chip scale packaging, CSP, high density via, interposer, low pitch via, through silicon via, wafer level packaging
The silicon via process developed by Silex offers sub 50 um via pitch for through wafer connections in up to 600 um thick wafers. Silex via process enables MEMS designs with significantly reduced die size and true “Wafer Level Packaging” – features that are particularly important in consumer market applications. The through wafer interconnect technology also enables integration of advanced interconnect functions in optical MEMS, sensors and microfluidic devices. With more than 10 foundry customers using the process today and an extraordinary line-up of potential users, Silex aims at making the process a standard in the MEMS industry. The swift propagation of the technology will be facilitated by reasonable licensing fees as well as technology transfer programs with customers who favor incorporating the technology in their existing manufacturing lines.
Journal: TechConnect Briefs
Volume: 3, Technical Proceedings of the 2007 NSTI Nanotechnology Conference and Trade Show, Volume 3
Published: May 20, 2007
Pages: 116 - 119
Industry sector: Sensors, MEMS, Electronics
Topic: Sensors - Chemical, Physical & Bio
ISBN: 1-4200-6184-4