Authors: H. Khan, D. Mamaluy and D. Vasileska
Affilation: Arizona State University, United States
Pages: 181 - 184
Keywords: FinFET, Quantum Transport, SCE, Process variation
We use Contact Block Reduction (CBR)method to investigate the critical issues relating optimization of device performance in 10 nm FinFET operating in ballistic regime. The goal of this work is to achieve the desired values of parameters characterizing device performance as projected by ITRS for double-gate high performance logic technology devices with physical gate length of nm. We also investigate the device characteristics due to process variation. The changes in device characteristics for fin width, oxide thickness, doping decaying slope, etc., varying within 10% of their desired values have been obtained. Slow process corner analysis (T = 110C and 10% reduction in the supply voltage) has also been performed to evaluate device performance in worst case operating condition. Simulation results show degradation in on-current, subthreshold slope, DIBL as well as cut-off frequency of the device. Our simulation results show that desired on-current and cut-off frequency can be achieved with a realistic doping profile.
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