Authors: M-W Ma, T-S Chao, K-S Kao, J-S Huang and T-F Lei
Affilation: National Chiao Tung University, Taiwan
Pages: 697 - 700
Keywords: high-k offset spacer, SOI, fringing electric field
In this paper, the 65-nm node SOI devices with high-k offset spacer was investigated. Calculated results show that the high-k offset spacer can effectively increase Ion and reduce Ioff due to the high vertical fringing field effect arising from the side capacitor comprising of gate/offset spacer/drain extension structure. This fringing field and, in turn, the Ion/Ioff current ratio and subthreshold swing can be strongly enhanced by increasing the dielectric constant of the offset spacer.