Authors: J. Liu, R. Weerasekera, L-R Zheng and H. Tenhunen
Affilation: Royal Institute of Technology (KTH), Sweden
Pages: 748 - 751
Keywords: nano modules and circuits, system level modeling, interconnect
we propose a bottom-up approach using nano-CMOS hybrid Autonomous Error-Tolerant (AET) cellular network architecture. In our approach, each hexagonal AET cell consists of a nano-core dedicated for local computing, CMOS cell peripherals responsible for cell I/Os and system level tasks, and their interface circuits. The idea is to partly move error and fault tolerance issues to system design and architecture level from today’s low level testing and testability design. The AET cells are physically autonomous and flexible. The overall network is homogenous (with identical cells) and constant-pattern symmetric wiring. These imply strict constraints for intercellular connection schemes. Despite of the locality of computing within each cell, the overall performance of the AET cellular network is very much dependent on the performance of the intercellular interconnects. We propose CMOS as cell I/Os for intercellular communications because its wires perform better than nano wires.