Authors: B. Mukherjee, P. Wang, L. Wang and A. Pacelli
Affilation: Stony Brook University, United States
Pages: 199 - 202
Keywords: inductance, interconnects, circuit extraction
We present a complete modeling technique for inductive parasitics, based on the vector potential equivalent circuit (VPEC) topology. Novel algorithms for layout extraction and sparsification are introduced. Examples are discussed in terms of CPU time, accuracy, and model complexity. Finally, extensions for high frequency applications are presented, including models for skin effect and full wave simulation.