Authors: T. Nakagawa, T. Sekigawa, T. Tsutsumi, E. Suzuki and H. Koike
Affilation: Electroinformatics Group, AIST, Japan
Pages: 330 - 333
Keywords: double-gate, MOSFET, modeling
Recently, a double-gate structure has attracted much attention as an emerging device concept. The DG MOSFET is regarded as the most scalable device. Usually the DG MOSFET is supposed to be used as a three-terminal transistor with one common gate. The alternative four-terminal operation mode with the independent front and back gate is promising. It enables dynamic fine-grain Vt control, and analog signal processing by using two gates. To evaluate the merit of these modifications on circuit design, a compact four-terminal DG MOSFET model is strongly needed. We consider fully depleted (FD) DG MOSFET with practical silicon channel thickness that ranges from 20nm down to 3nm. Although the range is not wide, the device physics changes drastically within this range. To make a compact model with these versatile requirements, the double charge-sheet model will be a good start point. In this model, carrier density of two charge sheets are calculated supposing the current which traverses between them is zero. In this poster presentation, we will address the issues on the compact model design of the four-terminal FD DG MOSFETs.
Nanotech Conference Proceedings are now published in the TechConnect Briefs