Nanotech 2003 Vol. 2

Technical Proceedings of the 2003 Nanotechnology Conference and Trade Show, Volume 2

Implications of Gate Tunneling and Quantum Effects in the Gate-Channel Stack

R. Dutton and C-H Choi

*Stanford University, US*

A Basic Property of MOS Transistors and its Circuit Implications

E. Vittoz, C. Enz and F. Krummenacher

*Swiss Center for Electronics & Microtechnology, CH*

USIM Design Considerations

A. Bell, K. Singhal and H. Gummel

*Agere Systems, US*

Theory, Development and Applications of the Advanced Compact MOSFET (ACM) Model

C. Galup-Montoro, M.C. Schneider, A.I.A. Cunha and O.C. Gouveia-Filho

*Universidade Federal de Santa Catarina, BR*

HiSIM: Accurate Charge Modeling Important for RF Era

M. Miura-Mattausch, D. Navarro, H. Ueno, H.J. Mattausch, K. Morikawa, S. Itoh, A. Kobayashi and H. Masuda

*Hiroshima University, JP*

An Advanced Surface-Potential-Plus MOSFET Model

J. He, X. Xi, M. Chan, A. Niknejad and C. Hu

*University of California at Berkeley, US*

A Technology-based Compact Model for Predictive Deep-Submicron MOSFET Modeling and Characterization

X. Zhou, S.B. Chiah and K.Y. Lim

*Nanyang Technological University, SG*

A Framework for Generic Physics Based Double-Gate MOSFET Modeling

M. Chan, Y. Taur, C.H. Lin, J. He, A. Niknejad and C. Hu

*Hong Kong University of Science & Technology, HK*

A Physics-Based Compact Model for Nano-Scale DG and FD/SOI MOSFETs

J. Fossum, L. Ge and M-H Chiang

*University of Florida, US*

BJT Modeling with VBIC, Basics and V1.3 Updates

C. McAndrew, T. Bettinger, L. Lemaitre and M. Tutt

*Motorola, US*

Compact Bipolar Transistor Modeling - Issues and possible solutions

M. Schroter

*University of Technology Dresden, DE*

Noise Modeling with MOS Model 11 for RF-CMOS Applications

A.J. Scholten, L.F. Tiemeijer, R. van Langevelde, R.J. Havens, A.T.A. Zegers-van Duijnhoven, V.C. Venezia and D. Klaassen

*Philips Research Laboratories Eindhoven, NE*

Physical Modeling of Substrate Resistance in RF MOSFETs

J. Han, M. Je and H. Shin

*Korea Advanced Institute of Science & Technology, KR*

Compact Modeling for RF and Microwave Integrated Circuits

A.M. Niknejad, M. Chan, C. Hu, B. Brodersen, J. Xi, J. He, S. Emami, C. Doan, Y. Cao, P. Su, H. Wan, M. Dunga and C.H. Lin

*University of California at Berkeley, US*

Vector Potential Equivalent Circuit for Efficient Modeling of Interconnect Inductance

A. Pacelli

*SUNY-Stony Brook, US*

A Physics-Based Analytical Surface Potential and Capacitance Model of MOSFET's Operation from the Accumulation to Depletion Region

J. He, X. Xi, M. Chan, K. Cao, A. Niknejad and C. Hu

*University of California, Berkeley, US*

Modeling of Direct Tunneling Current in Multi-Layer Gate Stacks

M.V. Dunga, X. Xi, J. He, I. Polishchuk, Q. Lu, M. Chan, A. Niknejad and C. Hu

*University of California, Berkeley, US*

Substrate Current in Surface-Potential-Based Compact MOSFET Models

X. Gu, H. Wang, T.L. Chen and G. Gildenblat

*Penn State University, US*

Application of Genetic Algorithm to Compact Model Parameter Extraction

X. Cai, H. Wang, X. Gu, G. Gildenblat and P. Bendix

*Penn State University, US*

A Surface-Potential-Based Compact Model of NMOSFET Gate Tunneling Current

X. Gu, H. Wang, G. Gildenblat, G. Workman, S. Veeraraghavan, S. Shapira and K. Stiles

*Penn State University, US*

Gate Current Partitioning in MOSFET Models for Circuit Simulation

Q. Ngo, D. Navarro, T. Mizoguchi, S. Hosakawa, H. Ueno, M. Miura-Mattausch and C.Y. Yang

*Santa Clara University, US*

Double-Gate CMOS Evaluation for 45nm Technology Node

M-H Chiang, J.X. An, Z. Krivokapic and B. Yu

*AMD, US*

Primary Consideration on Compact Modeling of DG MOSFETs with Four-terminal Operation Mode

T. Nakagawa, T. Sekigawa, T. Tsutsumi, E. Suzuki and H. Koike

*Electroinformatics Group, AIST, JP*

A Compact Model Methodology for Device Design Uncertainty

R. Williams, J. Watts, M-H Na, K. Bernstein

*Internatoinal Business Machines Corporation, US*

Unified Length-/Width-Dependent Threshold Voltage Model with Reverse Short-Channel and Inverse Narrow-Width Effects

S.B Chiah , X. Zhou and K.Y. Lim

*Nanyang Technological University, SG*

Unified Length-/Width-Dependent Drain Current Model for Deep-Submicron MOSFETs

S.B Chiah , X. Zhou and K.Y. Lim

*Nanyang Technological University, SG*

An Interactive Website as a Tool for CAD of Power Circuits

B. Swiercz, L. Starzak, M. Zubert and A. Napieralski

*Technical University of Lodz, PL*

Multidimensional Model-Based Parameter Estimation Method for Compact Modeling of High-Speed Interconnects

T. Dhaene

*University of Antwerp, BE*

An Automatic Macro Program developed for Characterization, Parameter Extraction and Statistic Analysis of Spiral Inductors

G.W. Huang, D.Y. Chiu and K.M. Chen

*National Nano Device Laboratories, TW*

Unified RLC Model for On-Chip Interconnects

S-P. Sim and C. Yang

*Santa Clara University, US*

Compact Modling of High Frequency Phenomena for On-Chip Spiral Inductors

N. Talwalkar, P. Yue and S. Wong

*Stanford University, US*

A Surface-Potential-Based Extrinsic Compact MOSFET Model

X. Gu, G. Gildenblat, G. Workman, S. Veeraraghavan, S. Shapira and K. Stiles

*Pennsylvania State University, US*

A Unified Environment for the Modeling of Ultra Deep Submicron MOS Transistors

T. Gneiting

*Advanced Modeling Solutions, DE*

Standardization of Compact Device moding in High Level Description Language

L. Lemaitre, C. McAndrew and W. Grabinski

*Motorola, CH*

Changing the Paradigm for Compact Model Integration in Circuit Simulators Using Verilog-A

M. Mierzwinsk, P.O. Halloran, B. Troyanovsky and R. Dutton

*Tiburon Design Automation, Inc., US*

ISBN: 0-9728422-1-7

Pages: 600

Nanotech Conference Proceedings are now published in the TechConnect Briefs