Authors: R.B. Iverson and Y.L. LeCoz
Affilation: Random Logic Corporation, United States
Pages: 117 - 121
Keywords: capacitance extraction, floating random-walk method, network reduction, RC extraction
The floating random-walk method has been used to efficiently extract interconnect capacitance in complex, multilevel integrated circuits. We present here an overview of the floating random-walk method in the context of capacitance extraction. The method implements a series of 3D random walks to statistically estimate elements of the capacitance matrix. Because the floating random-walk method reqmres no numerical mesh, excellent computational efficiency is achieved. The method is well suited for parallel implementation in possible full-chip applications. We describe, as well, a related methodology for extracting RC-interconnect parameters. Our methodology consists of conversion of the IC layoutdata into 3D structures, recognition of interconnects and devices, identification of interconnects requiring RC modeling, creation and simplification of RC models, and generation of a interconnect netlist.
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