Authors: M. Khan, S.B. Bollepalli and F. Cerrina
Affilation: UW-Madison, United States
Pages: 41 - 46
Keywords: dissolution, lithography
In this paper, we present a new resist dissolution model suitable for large range of application domains - from memory devices employing < 130nm design rules to MEMS devices with design rules exceeding 10s of microns. The proposed model uses empirical data such as "bulk" dissolution rate, and can be further tuned by other resist characterization studies such as depth and feature-size dependence of dissolution rate. The model can also take into account "local" properties such as developer concentration during the development process. The model uses the Fost Marching level Set technique to track the developer-resist interface. We discuss the dissolution model and its numerical implementation in detail and present the experimental techniques used to characterize the resist dissolution process, the data from which is then used to tune the dissolution model. We also present modeling results for a wide range of feature sizes and aspect ratios. We also present a "virtual development tool" that animates the 3D development process via an interactive graphical user interface shown in Figure 1.