Authors: S.B. Chiah, X. Zhou, K.Y. Lim, A. See and L. Chan
Affilation: Nanyang Technological University, Singapore
Pages: 750 - 753
Keywords: deep-submicron MOSFET, compact model, parameter extraction, nonlinear regression, optimization
This paper demonstrates a physically-based approach to parameter extraction of the compact Ids model we have developed for deep-submicron technology development. A two-iteration parameter-extraction scheme is described, which improves the previous one-iteration approach. Parameter calibration for the Vt model is revisited. Comparison of parabolic and linear body-bias dependency with new calibration sequence for the Vt model is carried out, which shows higher accuracy in Vt modeling for the new parabolic interpolation. Optimization for the halo pileup centriod, LDD lateral diffusion as well as saturation velocity is carried out to improve the overall Vt and Ids modeling. This has been verified with the experimental data from a 0.18-µm CMOS technology wafer.
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