Authors: R. Suaya
Affilation: Mentor Graphics, France
Pages: 722 - 725
Keywords: interconnect modeling, high speed digital circuits, RLC coupling
The modelisation of capacitance and inductance of wires for timing and noise simulation of digital circuits is discussed. Different domains characterized by the length of the wires and the driving strength require different approximations in the representation of the parasitic parameters. A modelisation methodology for interconnect parasitics is emerging.
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