Papers:
Challenges of Modeling VLSI Interconnects in the DSM Era
As VLSI technology shrinks to deep sub-micron (DSM) geometries (below 0.18mm), the parasitic due to interconnects are becoming a limiting factor in determining circuit performance. An accurate modeling of interconnect parasitic resistance (R), capacitance (C) [...]
Standardization and Validation of Compact Models
The idea of standardizing compact (SPICE-like) models has recently gained momentum in the semiconductor industry. However, since compact model equations reside in software, the concept of standardization is difficult. Several key issues must be addressed, [...]
Overview of An Advanced Surface-Potential-Based MOSFET Model (SP)
This paper outlines a new surface-potential-based compact MOSFET model (SP) developed at The Pennsylvania State University. The main objective of this work is to find practical engineering solutions of several long-standing problems of surface-potential-based modeling [...]
Engineering BSIM for the Nano-Technology Era and Beyond
This paper presents the current status of the forth generation BSIM model and issues of modeling CMOS based devices with nanometer dimensions. Due to the divergence of device structures in sub-0.1 m gate length, it [...]
The Foundations of the EKV MOS Transistor Charge-Based Model
Enz C., Bucher M., Porret A.S., Sallese J.M., Krummenacher F., Swiss Center for Electronics and Microtechnology, CH
This paper presents the foundations that lead to the EKV MOS transistor compact model. It describes all the basic concepts required to derive the large-signal and smallsignal charge-based model that is valid in all modes [...]
The EKV 3.0 Compact MOS Transistor Model: Accounting for Deep-Submicron Aspects
Bucher M., Enz C., Krummenacher F., Sallese J.M., Lallement C., Porret A.S., National Technical University of Athens, GR
The EKV 3.0 compact MOS transistor model for advanced IC design is presented. Its basis is an ideal analytical charge-based model including static to non-quasistatic dynamic aspects and noise. The ideal model is extended to [...]
RF Applications of MOS Model 11
van Langevelde R., Scholten A.J., Tiemeijer L.F., Havens R.J., Klaassen D.B.M., Philips Research Laboratories, NL
RF-CMOS applications impose increasingly stringent requirements on compact models used in circuit simulation. In this paper several of these issues will be addressed together with a discussion of the state-of-the-art of compact modelling.
HiSIM: Self-Consistent Surface-Potential MOS-Model Valid Down to Sub-100nm Technologies
Miura-Mattausch M., Ueno H., Mattausch J.H., Miura-Mattausch M., Kumashiro S., Yamaguchi T., Yamashita K., Nakayama N., Hiroshima University, JP
Surface-potential-basedMOSFET modeling is shown to be the right direction. Model parameters reflect the physical device parameters of advanced technologies directly, and can therefore be even scalable with technology changes. These advantages are demonstrated with HiSIM, [...]
Starting Over: gm/Id-Based MOSFET Modeling as a Basis for Modernized Analog Design Methodologies
A method of interpreting MOSFET behavior is described which is more coherent for modern analog CMOS circuit design. This method supercedes the use of simple but antiquated equations in design, and replaces them with an [...]
A Unified Process-Based Compact Model for Scaled PD/SOI and Bulk-Si MOSFETs
A process/physics-based compact model (UFPDB), unified for PD/SOI and bulk-Si MOSFETs with a single small set of parameters, is overviewed. The utility of UFPDB, e.g., for benchmarking PD/SOI and bulk-Si CMOS and for projecting performances [...]
Present Status and Future Direction of BSIM SOI Model for High-Performance/Low-Power/RF Application
The recent progress of BSIM (Berkeley Short-channel IGFET Model) SPICE models extended for SOI transistors are reviewed. The models cover partially depleted (PD), fully depleted (FD) and dynamic depletion (FD) (automatically transition between PD and [...]
RF MOSFET Noise Parameter Extraction and Modeling
In this paper, a novel procedure for extracting the important noise sources in MOSFETs is reviewed. Examples of extracted noise sources as a function of frequency, bias and geometry are presented using devices from a [...]
CMOS RF Modeling and Parameter Extraction Approaches Taking Charge Conservation into Account
A charge conserving small-signal equivalent circuit with very simple and accurate parameter extraction method for a three-terminal CMOS RF model is presented. We found that significant errors in circuit performances can be obtained if charge [...]
Automatic Generation of RF Compact Models from Device Simulation – Part I: Motivation and methodology
We review a recently proposed methodology for automatic generation of equivalent circuits from physical device simulation. The method is based on the calibration of a simplified equivalent-circuit model on simulation results, and can achieve an [...]
Xsim: A Compact Model for Bridging Technology Developers and Circuit Designers
This paper describes the ideas and philosophy behind a new compact model (CM) for deep-submicron MOSFETs, called Xsim, which has been developed from scratch over the past few years. Similarities to and differences from existing [...]
Unified Statistical Modeling for Circuit Simulation
Accurate statistical simulation and modeling are important for IC design. Different types of statistical simulation require different types of statistical models. In this paper a unified approach to statistical modeling and characterization is presented. Based [...]
The Role of TCAD in Compact Modeling
This paper is an introduction to semiconductor process and device simulation and its role in compact modeling for circuit simulation. A brief history of TCAD is given. One use of TCAD is in the generation [...]
Interconnect Modeling for High Speed Digital Circuits – the Role of RLC Coupling
The modelisation of capacitance and inductance of wires for timing and noise simulation of digital circuits is discussed. Different domains characterized by the length of the wires and the driving strength require different approximations in [...]
How to Build an SOI MOSFET Compact Model without Violating the Laws of Physics
An important application for partially depleted SOI is high performance microprocessors and other logic chips. In order to deliver market leading performance it is necessary for transistor design and circuit design to be done concurrently. [...]
Methodology for Model Generation with Accuracy from DC to RF
This paper presents an example modeling flow for generating a RF CMOS model. Initially, the objectives of this modeling approach are analyzed. Then issues in test structure design are discussed. In the section of model [...]
Measurements and Modeling of Mobility in Ultra-Thin SOI
We present a study of the effective mobility (ueff) of ultra thin SOI n MOSFETs for both single and double gate operation. Electron mobility was measured for silicon thickness Tsi down to approximately 5 nm [...]
A New Analytical Model of Channel Hot Electron (CHE) and CHannel Initiated Secondary ELectron (CHISEL) Current Suitable for Compact Modeling
This paper presents for the first time a new approach to hot-carrier phenomena leading to an analytical model of both Channel Hot Electron (CHE) and CHannel Initiated Secondary ELectron (CHISEL) currents. This model can be [...]
Simulation Study of Non-Quasi Static Behaviour of MOS Transistors
In this paper, we study the "non-quasi static" (NQS) behaviour of MOS transistors using an exact quasi static Look-up Table (LUT) [1] MOSFET model implemented in a general-purpose circuit simulator SEQUEL [2], device simulator ISE-TCAD [...]
Compact Model for Manufacturing Design and Fluctuation Study
In this article, a physics based compact model [1, 2] has been used as a tool for manufacturing process variability study. Three critical end-of-line (EOL) measured electrical testing (ET) parameters, namely Vth, Ion and Ioff, [...]
Physically-Based Approach to Deep-Submicron MOSFET Compact Model Parameter Extraction
This paper demonstrates a physically-based approach to parameter extraction of the compact Ids model we have developed for deep-submicron technology development. A two-iteration parameter-extraction scheme is described, which improves the previous one-iteration approach. Parameter calibration [...]
New Compact Model for Generation Drain Current Transients in Weak and Moderate Inversions of Submicron Floating-Body PD SOI MOSFETs
In this paper, generation-type drain current transients, in advanced (down to 50nm gate-length) floating-body PD SOI MOSFETs are investigated by 2D numerical simulation in weak inversion operation. An original compact analytical model is derived for [...]
Journal: TechConnect Briefs
Volume: 1, Technical Proceedings of the 2002 International Conference on Modeling and Simulation of Microsystems
Published: April 22, 2002
Industry sector: Sensors, MEMS, Electronics
Topic: Compact Modeling
ISBN: 0-9708275-7-1