Nanotech 2001 Vol. 1
Nanotech 2001 Vol. 1
Technical Proceedings of the 2001 International Conference on Modeling and Simulation of Microsystems

Compact Modeling and Model Order Reduction Chapter 3

A New Compact Model of Floating Gate Non-Volatile Memory Cells

Authors: L. Larcher, P. Pavan, F. Gattel, L. Albani and A. Marmiroli

Affilation: Università di Modena e Reggio Emilia, Italy

Pages: 56 - 59

Keywords: device and circuit simulation, floating gate devices, nonvolatile memories

This paper presents a new compact model of Floating Gate Non-Volatile Memory Cells using SPICE circuit elements. It features many advantages compared to previous models: it is simple and easy to implement and to update, scalable, and its computational time is not critical, thus making it very attractive to industry. It is based on a new procedure which estimates the floating gate voltage without using fixed capacitive coupling coefficients, thus improving its simulation capability. MOreover, since this model requires only standard parameters extracted for SPICE-like models of MOS transistors (plus the floating gate to control gate capacitance), any industry CMOS parameter extraction procedure should be applied to the dummy cell (where the control gate and the floating gate are short-circuited). This model can be easily used both in device optimization and in circuit performance evaluation.

ISBN: 0-9708275-0-4
Pages: 638