Authors: A. Yip, Y.T. Yeow, G.S. Samudra and C.H. Ling
Affilation: TECH Semiconductor, Singapore
Pages: 360 - 363
Keywords: MOSFET, hot-carrier effects, interface traps, gated-diode, simulation
A study of the “gated-diode” configuration in MOSFET’s for characterising hot-carrier degradation by employing 2-D simulations is presented in this paper. We use both process and device simulations to understand operational sensitivity of this technique. The parameters involved in the gated-diode measurement like recombination processes and carrier concentrations, which are not available from experiments, will be discussed. The interface trap distribution across the bandgap and spatial distribution are also explored here. In addition, the gated-diode measurement method is modelled with specific task of determining interface state density.