Authors: V. Gupta and T. Mukherjee
Affilation: Carnegie Mellon University, United States
Pages: 150 - 153
Keywords: synthesis, CAD, CMOS MEMS accelerometer
An optimal layout synthesis methodology for CMOS MEMS accelerometers is presented. It consists of a parame-trized layout generator that optimizes design objectives while meeting functional specifications. The behavior of the device is estimated using lumped parameter analytical equa-tions. The design problem is then formulated into a non-lin-ear constrained optimization problem. Such an approach to automated design of MEMS devices helps the designer to explore design trade-offs efficiently. Synthesis of cell level devices is also required for structured design of integrated MEMS. Designs for a CMOS MEMS accelerometer for dif-ferent optimization objectives, as well as possible design trade-offs are discussed.
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