Authors: W.T. Lynch
Affilation: Independent Consultant, United States
Pages: 75 - 78
Keywords: interconnect, repeaters, copper, ICs, wiring
For the first time a comprehensive methodology has been applied to the pre-physical design of hierarchical interconnect wiring with consideration of the limitations of both the device and the wiring technologies (Fig. 1). The overall goal is an optimized distribution of power supplies and clocks, inclusive with a histogram-based decision algorithm for general wiring [2,3]. The specific goal is the use of a minimum number of wiring levels, with wiring sizes that achieve the performance requirements. Decision criteria are established for the insertion of repeaters by means of a normalized comparison of trombone-staged drivers, single-stage inverting repeaters, and two-stage non-inverting repeaters (Fig. 3), as well as for Al vs. Cu options. When the repeaters are optimized to minimize delay, the MOSFET r0 and c0 device parameters are no less than equally important to the per unit wiring length values for RL and CL. The fundamental delay inhibitors are the MOSFET Isat/Cgate slew rate (V/s) and the nodal wire length L.