Authors: O. Kwon, S. Yoon, Y. Ban and T. Won
Affilation: Inha University, Korea
Pages: 688 - 691
Keywords: modeling, topography, deposition, etching, process simulation, process integration, parallel computation, DRAM
In this paper, we present a 3D topography simulator, so-called 3D-SURFILER(SURface proFILER), to model a complicated 3D structure on the substrate for gigabit DRAMs. The 3D-SURFILER comprises a deposition and etching simulator employing a cell advancing scheme and a parallel computational numerical engine. An MIM (Metal-Insulator-Metal) stacked capacitor  has been chosen to verify the validity of the simulator.
Nanotech Conference Proceedings are now published in the TechConnect Briefs