Index of Keywords


Compact Analytical Threshold Voltage Model for Nanoscale Multi-Layered-Gate Electrode Workfunction Engineered Recessed Channel (MLGEWE-RC) MOSFET

An Analytical Solution to a Double-Gate MOSFET with Doped Body

Atomistic Electrostatic Simulations Using Spice

Interface Traps in Surface-Potential-Based MOSFET Models

Analytic MOSFET Surface Potential Model with Inclusion of Poly-Gate Accumulation, Depletion, and Inversion Effects


A Scalable POWER MOSFET Model with an Integrated Body-Diode Including Reverse Recovery


RF Modeling of 45nm Low-Power CMOS Technology

1/f Noise Modeling at Low Temperature with the EKV3 Compact Model

SPICE BSIM3 Model Parameters Extraction and Optimization for Low Temperature Application


An SOA Aware MOSFET Model for Highly Integrated, Analog Mixed-Signal Design Environments


Impact of Gate-Induced-Drain-Leakage current modeling on circuit simulations in 45nm SOI technology and beyond

Electrostatic Potential Compact Model for Symmetric and Asymmetric Lightly Doped DG-MOSFET Devices

Source/Drain Edge Modeling for DG MOSFET Compact Model

Xsim: Benchmark Tests for the Unified DG/GAA MOSFET Compact Model

Improved Compact Model of Quantum Sub-band Energy Levels for MOSFET Device Application

The Effects of gamma-ray Radiation on n-channel MOSFET

Compact Models for sub-22nm MOSFETs

Xsim: A Unified Compact Model for Bulk/SOI/DG/GAA MOSFETs

Drain Induced Barrier Lowering (DIBL) Effect on the Intrinsic Capacitances of Nano-Scale MOSFETs

Single-walled Carbon Nanotube (CNT) Field Effect Transistor Device Modeling