NSTI Nanotech 2009

Analytical Modelling of Ballistic and Quasi-Ballistic Nanowires:Validation and Application to CMOS Architecture

S. Martinie, D. Munteanu, G. Le Carval, M.-A. Jaud, J.L. Autran
CEA, LETI, Minatec, FR

Keywords: nanowire, ballistic transport, quasi-ballistic transport, CMOS inverter


We present here an unified analytic model for ballistic and quasi-ballistic Silicon Nanowire (SNW represented in figure 1). Starting from the classical flux method and using the Lundstrom/Natori approaches [1-2], we enhanced them by taking into account carrier degeneracy and an original modelling of Short Channel Effect (SCE) and Drain Induced Barrier Lowering (DIBL). Our model has been validated by comparisons with numerical simulations [3]. Finally, we implemented our model in a Verilog-A environment and we applied it to simulate simple circuit elements to evaluate potential performance of a Silicon Nanowire architecture.
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