2008 NSTI Nanotechnology Conference and Trade Show - Nanotech 2008 - 11th Annual

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TechConnect Summit
Clean Technology 2008

Stress-induced Effects on the Depletion Layer Capacitance of Silicon

K. Matsuda, Y. Kanda, Y. Itoh
Tokushima Bunri University at Kagawa, JP

capacitance, stress, depletion, piezo

Stress-induced effect on resistance of silicon has been extensively investigated to explore high speed semiconductor devices, whereas there have been few reports about stress-induced effect on the parastic capacitance although it becomes important as the semiconductor devices scale down and the switching speed of logic gate becomes higher. Recently, we discovered abrupt large shifts in the capacitance on the inversion regim of MOSFET by applying uniaxial stress at room temperature. Gauge factor of the effect are almost comparable with the piezoresistance effect, so ite has been called piezocapacitance effect in the depletion layer since then. The piezocapacitance effect can be explained with the shift in the intrinsic Fermi level attributed to the DOS change as well as the band gap narrowing according to the deformation potential theory of Herring and Vogt. On the base of the model, we will show other strain-induced effects on the depletion layer capacitance of silicon and discuss with the experimental data.

Nanotech 2008 Conference Program Abstract