2008 NSTI Nanotechnology Conference and Trade Show - Nanotech 2008 - 11th Annual

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Clean Technology 2008

A Practical High-Voltage MOS Model with SOA Representation and Predictability

A. Young, J. Hall, Z. Luo
Fairchild Semiconductor, US

BSIM, model, LDMOS, HVMOS, SOA, breakdown, warning, simulation, spectre, contour

Circuit simulations involving power devices often require additional checks compared with generic low-power applications. This additional burden lies with the individual designer to ensure that the power transistor(s) are operating well within the Safe Operating Area (SOA). However, it is not trivial to perform such checks due to the inherit limitations of the industry standard BSIM MOS models: inadequate diode model for the junctions, non-existence of junction breakdowns, and alert when such breakdown voltages are reached. For large circuits, it is inefficient to manually check all power devices are within the SOA. We have demonstrated a Sub-Circuit, BSIM based, Power MOSFET Model with a behavioral current source conforming to the SOA contour extracted from the pulse measurements, along with a warning system built-in to the Cadence Spectre Simulator, the designer will be able to catch both transient spikes and dynamic breakdowns (function of Vgs and Vds) outside of the MOSFET’s SOA; both by an output log of errant circuit nodes and the associated time intervals where they are outside of the SOA region, and visually where the breakdown anomalies are observable due to the behavioral current source within the Sub-Circuit Model. This methodology can be easily generalized to other devices for the circuits of interest.

Nanotech 2008 Conference Program Abstract