2008 NSTI Nanotechnology Conference and Trade Show - Nanotech 2008 - 11th Annual

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TechConnect Summit
Clean Technology 2008

Source/Drain Junction Partition in MOS Snapback Modeling for ESD Simulation

Y. Zhou, J.-J. Hajjar
Analog Devices, Inc., US

ESD MOS model

A new enhancement on modeling ‘snapback’ in MOS transistors for ESD simulation is presented. The model uses standard industry models only and intrinsically includes all major physical effects in snapback. An ESD snapback MOS model is typically an extension of the standard MOS model with a BJT, a current source and a resistor. The typical resistance value is several hundred Ohms. However, the resistance between the Drain and Body is only a few Ohms when it is measured with the junction forward biased. Additionally, the extracted capacitance value of the junction from the dV/dt effect is significantly smaller than the value measured directly at the junction. Moreover, the base current in the parasitic BJT indicates much higher resistance in simulation than in measurement. The fact that only a portion of the Drain and Source junctions contribute to the parasitic BJT causes the above three discrepancies. Therefore, the MOS snapback model is enhanced by partitioning the Drain and Source junctions so that only a portion of them are included in the parasitic BJT. Two diodes are added to the typical model equivalent circuit. The comparison of simulation and measured data of a Grounded-Gate NMOS shows good agreement for both positive and negative drain voltage stresses. The simulation for the base current curve of the parasitic bipolar shows significant improvement as well.

Nanotech 2008 Conference Program Abstract