2008 NSTI Nanotechnology Conference and Trade Show - Nanotech 2008 - 11th Annual

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Clean Technology 2008

Multi-Bit/Cell SONOS Flash Memory with Recessed Channel Structure

K-R Han, H-I Kwon, J-H Lee
Kyungpook National University, KR

multi-bit/cell, recessed channel, sensing margin, SONOS, flash, memory

A novel device structure for 4-bit/cell with recessed channel structure is presented and characterized for NOR-type nonvolatile memory (NVM) technology. In this paper, we studied a 4-bit/cell SONOS flash memory cell Since two transistors in a recessed region share the gate and the source, integration density could be very high (~3 times compared to conventional 60 nm NOR cell). It is similar to vertical channel structure, but originated recessed channel structure. Using channel hot electron (CHE) injection, we observed successfully threshold voltage window and sensing margin of 2.8 and 2.34 V to 2-bit/cell operation. We also have shown there is no interference between storage nodes in a cell. Especially, the cell size is possible to shrink 1.25F2/bit in a 4-bit/cell. Our proposed device structure can be one of most promising candidates for multi-bit operation scaled NVM technology.

Nanotech 2008 Conference Program Abstract