2007 NSTI Nanotechnology Conference and Trade Show - Nanotech 2007 - 10th Annual

MOS Structures Containing Amorphous Silicon Nanoparticles for Application in Memory Devices

N. Nedev, M. Stoytcheva, D. Nesheva, E. Manolov, R. Brüggemann, Z. Levi, R. Zlatev, B. Valdez and L. Alvarez
Universidad Autónoma de Baja California, MX

amorphous Si nanoparticles, memory devices

Metal-Oxide-Silicon structures containing a layer with amorphous silicon nanoparticles in a silicon oxide matrix are fabricated by sequential physical vapour deposition of SiOx (x=1.15) and RF sputtering of SiO2 on n-type crystalline silicon, followed by high temperature annealing in an inert gas ambient at 700o C. The annealing process is used not only for phase separation, growing of amorphous silicon nanoparticles in a dielectric matrix, but also for formation of a few nanometers thick insulating layer between the nanoparticles and the silicon substrate. High frequency C-V measurements demonstrate that the structures can be charged negatively or positively by applying a positive or negative voltage on the gate. The structures with amorphous silicon nanoparticles show several important advantages compared to structures fabricated using similar technological steps, but which contain Si nanocrystals; i.e. lower defect density at the interface between the crystalline silicon wafer and the tunnel silicon oxide, better reliability and the most essential one – better retention characteristics.

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Nanotech 2007 Conference Program Abstract


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