2007 NSTI Nanotechnology Conference and Trade Show - Nanotech 2007 - 10th Annual

CMOS Process and Design Options for 32nm and beyond

A. Wild
Freescale Semiconductors Crolles Research Center, FR

CMPS, 32 nm, nanotechnology

Continuing inexorably along the CMOS scaling roadmap, it is essential to recognize the points at which the existing patterning techniques, gate stack materials, device architectures, interconnect solutions, etc. cannot be refined any further and radical changes become unavoidable. A new challenge is the increasing difficulty to keep the tolerances of all kind under control, and a specific response is to tightly connect design and process to improve manufacturability. This talk is exploring some candidates already identified as possible solutions enabling continued scaling.

Back to Program

Sessions Sunday Monday Tuesday Wednesday Thursday Authors Keywords

Nanotech 2007 Conference Program Abstract


Names, and logos of other organizations are the property of those organizations and not of NSTI.
This event is not open to the general public and NSTI reserves the right to refuse admission and participation to any individual.