2007 NSTI Nanotechnology Conference and Trade Show - Nanotech 2007 - 10th Annual

An Integrate and Fire Spiking Neuron Using Silicon Nano-Wire Technology

A. Bindal and S. Hamedi-Hagh
San Jose State University, US

silicon nano wire, silicon nano wire transistor, nano wire, nano wire transistor

This study presents a nanometer-scale Integrate and Fire Spike (IFS) neuron cell using vertically-grown, undoped silicon nano-wire transistors. The design cycle starts with determining individual metal gate work functions for each NMOS and PMOS transistor to produce a 300mV threshold voltage. Wire radius and effective channel length are varied to find a common body geometry that yields smaller than 1pA OFF current and produces maximum ON currents for both transistors. Once the optimal device dimensions are defined, a spike neuron cell is built; its transient performance, power dissipation and layout area are measured. Post-layout simulation results indicate that worst-case power dissipation of the neuron is 1.44µW if a single synapse is connected at its output and increases by 18nW per synapse at 500MHz. The neuron circuit occupies approximately 0.116µm2.

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