2007 NSTI Nanotechnology Conference and Trade Show - Nanotech 2007 - 10th Annual

Low-voltage pentacene thin film transistors with ultra thin SiO2 and SiON gate dielectrics

S.W. Cho, D.S. Park, W.C. Chang, K.-H. Yoo, K. Jeong, C.-N. Whang, Y. Yi, K.B. Chung and M.-H. Cho
Yonsei University, KR

OTFTs; pentacene; Photoemission; interface dipole; band diagram

We report on the fabrication of pentacene-based thin-film transistors (TFTs) with ultra thin (4.5 nm) SiO2 and SiON gate dielectric layers for low-voltage operations. The device with the SiON as a gate dielectric layer was operated at a gate voltage lower than 3.0 V, showing a threshold voltage of 0.45 V, which is much lower than the threshold voltage of the SiO2 device ( 2.5 V). The electronic structures at the interface region between the pentacene and the dielectric layers were investigated by in situ ultraviolet photoelectron spectroscopy (UPS) and x-ray photoelectron spectroscopy (XPS) to find the origin of the lower operating voltage. The magnitude of the interface dipole and the band bending at the interface was determined, and the complete energy level diagrams for pentacene on SiO2 and SiON were evaluated. The interface dipole modifies the surface potential of the dielectric layer next to the transistor. The shift of the threshold voltage and the turn-on voltage were explained using the energy level diagram.

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