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Program Committee

2007 Workshop on

Compact Modeling

WCM 2007

in Association with

Tenth International Conference on
Modeling and Simulation of Microsystems

MSM 2007

May 20-24, 2007
Santa Clara Convention Center
Santa Clara, California, U.S.A.

Workshop Chair

Xing Zhou Xing Zhou
Nanyang Technological University, Singapore


Compact Models (CMs) for circuit simulation have been at the heart of CAD tools for circuit design over the past decades, and are playing an ever increasingly important role in the nanometer system-on-chip (SOC) era. As the mainstream MOS technology is scaled into the nanometer regime, development of a truly physical and predictive compact model for circuit simulation that covers geometry, bias, temperature, DC, AC, RF, and noise characteristics becomes a major challenge.

Workshop on Compact Modeling (WCM) is one of the first of its kind in bringing people in the CM field together. The objective of WCM is to create a truly open forum for discussion among experts in the field as well as feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development and deployment, within the main theme - compact models for circuit simulation:

  • Bulk MOS intrinsic models
  • SOI/double-gate/multiple-gate/floating-gate MOS models
  • Bipolar/HBT/SiGe/GaN/JFET models
  • RF/noise/scalable capacitance/NQS models
  • Statistical/predictive/process-based models
  • Interconnection/passive device models
  • Extrinsic/parasitic element models
  • Reliability/hot carrier/tunneling/ESD models
  • Atomic-level/quantum-mechanical compact models
  • Numerical/TCAD/behavioral/table-based models
  • Model parameter extraction and optimization
  • Model-simulator interface and standardization


Invited Speakers

Invited speakers from all over the world are listed below:

  • Narain Arora, Cadence Design Systems, USA
  • Matthias Bucher, Technical University of Crete, Greece
  • Mansun Chan, Hong Kong University of Science and Technology, Hong Kong
  • Zuhui Chen, Xiamen University, China
  • Jamal Deen, McMaster University, Canada
  • Robert Dutton, Stanford University, USA
  • Tor Fjeldly, Norwegian University of Science and Technology, Norway
  • Jerry Fossum, University of Florida, USA
  • Carlos Galup-Montoro, Universidade Federal de Santa Catarina, Brazil
  • Chenming Hu, University of California at Berkeley, USA
  • Benjamín Iñíguez, Universitat Rovira i Virgili, Spain
  • Bin Jie, Peking University, China
  • Dirk Klaassen, NXP Semiconductors, The Netherlands
  • Mark Lundstrom, Purdue University, USA
  • Colin McAndrew, Freescale Semiconductor, USA
  • Mitiko Miura-Mattausch, Hiroshima University, Japan
  • Adelmo Ortiz-Conde, Universidad Simón Bolívar, Venezuela
  • Chih-Tang Sah, University of Florida, USA
  • Michael Schröter, University of Technology Dresden, Germany
  • Yuan Taur, University of California at San Diego, USA
  • Josef Watts, IBM, USA
  • Philip Wong, Stanford University, USA
  • Xing Zhou, Nanyang Technological University, Singapore


Workshop Program

 Click on each  to download a PDF file of the presentation. © Copyright of the PDF files belongs to the respective contributors.

Tuesday May 22

7:00 TUESDAY - Registration
8:30 WCM: Bulk MOS Intrinsic Models
10:30 WCM: Bulk MOS intrinsic/interface models
1:30 WCM: Double/multiple-gate MOS models
4:00 WCM: Double/multiple-gate MOS models

Wednesday May 23

8:30 WCM: Atomic/numerical-based models
10:30 WCM: Statistical/process-based models
1:30 WCM: SOI/double-gate/high-voltage models
2:00 Nanotech Poster Session 2 - Expo Reception (2:00 - 4:00)
4:00 WCM : Poster Briefing 1
5:10 WCM : Poster Briefing 2

Thursday May 24

8:00 WCM: Special Overview
8:30 WCM: Interconnect/parasitic/process models
10:30 WCM: FET/HBT models

Tuesday May 22

Back to Top
7:00 TUESDAY - RegistrationMain Lobby
Back to Top
8:30 WCM: Bulk MOS Intrinsic ModelsGrand Ballroom A
 Session chair: Xing Zhou, Nanyang Technological University, Singapore
8:30 Design-Oriented Characterization and Parameter Extraction Methodologies for the EKV3 MOSFET Model
M. Bucher, A. Bazigos, D. Diamantakos and F. Krummenacher, Technical University of Crete, GR (invited)
9:00 Consistency of compact MOSFET models with the Pao-Sah formulation: consequences for small-signal analysis
C. Galup-Montoro, M.C. Schneider and A.I.A. Cunha, Federal University of Santa Catarina, BR (invited)
9:30 HiSIM2.4.0: Advanced MOSFET model for the 45nm Technology Node and Beyond
M. Miura-Mattausch, N. Sadachika, M. Miyake, D. Navarro, T. Ezaki and H.J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Miyamoto, R. Inagaki and Y. Furui, Hiroshima University, JP (invited)
Back to Top
10:30 WCM: Bulk MOS intrinsic/interface modelsGrand Ballroom A
 Session chair: Mitiko Miura-Mattausch, Hiroshima University, Japan
10:30 A History of Electronic Traps on Silicon Surfaces and Interfaces
C-T Sah, B.B. Jie and Z. Chen, University of Florida, US (invited)
11:00 High Conentration of Interface Traps in MOS Transistor Modeling
Z. Chen, B.B. Jie and C-T Sah, Xiamen University, CN (invited)
11:30 Analytical Solutions for Long-Wide-Channel Thick-Base MOS Transistors I. Effects of Remote Boundary Conditions and Body Contacts
B.B. Jie and C-T Sah, Peking University, CN (invited)
Back to Top
1:30 WCM: Double/multiple-gate MOS modelsGrand Ballroom A
 Session chair: Dirk Klaassen, NXP Semiconductors, the Netherlands
1:30 Compact Modeling Framework for Short-Channel DG and GAA MOSFETs
H. Børli, S. Kolberg and T.A. Fjeldly, Norwegian University of Science and Technology, NO (invited)
2:00 Modeling of Saturation-Region Characteristics of Nanoscale Double-Gate MOSFETs
J.G. Fossum and S. Chouksey, University of Florida, US (invited)
2:30 A Versatile Multigate MOSFET Compact Model: BSIM-MG
C. Hu, M. Dunga, C-H. Lin, D. Lu, A. Niknejad, University of California, Berkeley, US (invited)
3:00 3-D Analytical Models for the Short-Channel Effect Parameters in Undoped FinFET Devices
H.A. Hamid, B. Iniguez and J. Roig, Universitat Rovira i Virgili, ES (invited)
Back to Top
4:00 WCM: Double/multiple-gate MOS modelsGrand Ballroom A
 Session chair: Tor Fjeldly, Norwegian University of Science and Technology, Norway
4:00 A PSP based scalable compact FinFET model
G.D.J. Smit, A.J. Scholten, N. Serra, R.M.T. Pijper, R. van Langevelde, A. Mercha, G. Gildenblat and D.B.M. Klaassen, NXP Semiconductors, NL (invited)
4:30 A Unified View of Drain Current Models for Undoped Double-Gate SOI MOSFETs
A. Ortiz-Conde and F.J. García Sánchez, Simón Bolívar University, VE (invited)
5:00 Analytic Charge Model for Double-Gate and Surrounding-Gate MOSFETs
B. Yu, H. Lu, W-Y Lu and Y. Taur, UCSD, US (invited)
5:30 Unified Compact Model for Generic Double-Gate MOSFETs
X. Zhou, G.H. See, G.J. Zhu, K. Chandrasekaran, Z.M. Zhu, S.C. Rustagi, S.H. Lin, C.Q. Wei and G.H. Lim, Nanyang Technological University, SG (invited)

Wednesday May 23

Back to Top
8:30 WCM: Atomic/numerical-based modelsGrand Ballroom A
 Session chair: Josef Watts, IBM, USA
8:30 Nanoscale Physics for Compact Models
M. Lundstrom and H. Pal, Purdue University, US (invited)
9:00 Carbon Nanotube Transistor Compact Model
J. Deng, G.C. Wan and H.-S. Wong, Stanford University, US (invited)
9:30 Modeling of FET Flicker Noise and Impact of Technology Scaling
C.-Y. Chen, Y. Liu, S. Cao, R. Dutton, J. Sato-Iwanaga, A. Inoue and H. Sorada, Stanford University, US (invited)
Back to Top
10:30 WCM: Statistical/process-based modelsGrand Ballroom A
 Session chair: Carlos Galup-Montoro, Universidade Federal de Santa Catarina, Brazil
10:30 Modeling MOSFET Process Variation using PSP
J.S. Watts, Y-M Lee and J-E Park, IBM, US (invited)
11:00 Modeling Process Variations Using a Compact Model
R. Murali and J.D. Meindl, Georgia Tech, US
11:20 Simulating CMOS Circuits Containing Multiple FET Types Including the Geometric Dependence of Correlation between FET Types
J-E Park, C-H Liang, J. Assenmacher, J. Watts, S-J Park and R. Wachnik, IBM, US
11:40 Optimal Skew Corners for Compact Models
N. Lu, IBM, US
Back to Top
1:30 WCM: SOI/double-gate/high-voltage modelsGrand Ballroom A
 Session chair: Keith Green, Texas Instruments, USA
1:30 Impact of Gate Induced Drain Leakage and Impact Ionization Currents on Hysteresis Modeling of PD SOI Circuits
Q. Chen, S. Suryagandh, J-S Goo, J.X. An, C. Thuruthiyil and A.B. Icel, Advanced Micro Devices, US
1:50 Compact modeling of drain current in Independently Driven Double-Gate MOSFETs
D. Munteanu, J.L. Autran, X. Loussier and O. Tintori, L2MP-CNRS, FR
2:10 Explicit Short Channel Compact Model of Independent Double Gate Mosfet
M. Reyboz, O. Rozeau, T. Poiroux, P. Martin, M. Cavelier and J. Jomaah, CEA-LETI, FR
2:30 A Computationally Efficient Method for Evaluating Distortion in DG MOSFETs
R. Salazar, A. Ortiz-Conde and F.J. García Sánchez, Solid State Electronics Laboratory, VE
Back to Top
2:50 WCM: Late NewsGrand Ballroom A
 Session chair: Xing Zhou, Nanyang Technological University, Singapore
Double-Gate Thin-Base MOS Transistor: The Correct Theory
C-T Sah and B.B. Jie, University of Florida, US
Double-Gate Thin-Base MOS Transistor: Characteristics for the Long Channel
B.B. Jie and C-T Sah, University of Florida, US
U-Shaped Engery Distribution of Electronic Interface Traps on Oxidized Silicon
Z. Chen, B.B. Jie and C-T Sah, University of Florida, US
Back to Top
2:00 Nanotech Poster Session 2 - Expo Reception (2:00 - 4:00)Exhibit Hall
Back to Top
4:00 WCM : Poster Briefing 1Grand Ballroom A
 Session chair: Brian Q. Chen, AMD, USA
4:00 A charge based compact flicker noise model including short channel effects
A.S. Roy and C.C. Enz, EPFL, CH
4:05 HiSIM-Varactor: Complete Surface-Potential-Based Model for RF Applications
M. Miyake, N. Sadachika, K. Matsumoto, D. Navarro, T. Ezaki, M. Miura-Mattausch, H.J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi and S. Miyamoto, Hiroshima University, JP
4:10 PTAT voltage generator based on an MOS voltage divider
C. Rossi, C. Galup-Montoro and M.C. Schneider, Universidad de la Republica, UY
4:15 LINFET: A BSIM class FET model with smooth derivatives at Vds=0
L. Wagner and C.M. Olsen, IBM Systems Technology Group, US
4:20 Charge-Based Threshold Voltage Definition for Undoped Single Gate and Symmetric Double Gate MOSFETs
C. Galup-Montoro, M.C. Schneider and A.I.A. Cunha, Universidade Federal da Bahia - UFBA, BR
4:25 A Carrier-Based Analytic Model for Undoped Ultra-Thin-Body Silicon-on-Insulator (UTB-SOI) MOSFETs
J. He, W. Bian, Y. Tao, B. Li and Y. Chen, Peking University, CN
4:30 An Explicit Carrier-Based Compact Model for Surrounding-Gate MOSFETs
J. He, F. Liu, W. Bian, Y. Tao, W. Wu, K. Lu, T. Wang and M. Chan, Peking University, CN
4:35 Body Bias Dependency of Substrate Current and Its Modeling for SOI Devices
Y. Ma, M-C Jeng and Z. Liu, Cadence Design System, Inc., US
4:40 Compact Models for Asymmetric Double Gate MOSFETs
H.C. Morris, H. Abebe and E.C. Cumberbatch, San Jose State University, US
4:45 Transition Point Consideration for Velocity Saturating Four-terminal DG MOSFET Compact Model
T. Nakagawa, T. Sekigawa, T. Tsutsumi, M. Hioki, S. O’uchi and H. Koike, AIST, JP
Back to Top
5:10 WCM : Poster Briefing 2Grand Ballroom A
 Session chair: Mansun Chan, Hong Kong University of Science and Technology, Hong Kong
5:10 An Efficient Sectionalized Modeling Approach for Introduction of Distributed Avalanche Effects in Bipolar Circuit Design
V. Milovanovic and S. Mijalkovic, Delft University of Technology, NL
5:15 A Setup for Automatic MOSFET Mismatch Characterization under a Wide Bias Range
H. Klimach, C. Galup-Montoro and M.C. Schneider, Federal University of Santa Catarina, BR
5:20 An Approximate Explicit Solution to General Diode Equation
J. He, Y. Tao, C. Yang, M. Feng, B. Li, W. Bian and Y. Chen, Peking University, CN
5:25 Methodology and Design Kit Integration of a Broadband Compact Inductor Model
M. Erturk, R. Groves and E. Gordon, IBM, US
5:30 A Compact Model for Temperature and Frequency Dependence of Spiral Inductor
Y.Z. Xu and J.T. Watt, Altera Corporation, US
5:35 SPICE Modeling of Hook Shaped Idsat Curve for I/O 2.5V MOS Transistors
P.B.Y. Tan, A.V. Kordesch and O. Sidek, Silterra Malaysia Sdn. Bhd., MY
5:40 HiSIM- Replacement of BSIM4 in UDSM Circuit Simulations
Y. Iino and I. Pesic, Silvaco Japan, JP
5:45 Process Aware Hybrid SPICE Models using TCAD and Silicon Data
Y. Mahotin, S. Tirumala, X. Lin and D. Pramanik, Synopsys Inc., US
5:50 Simulation of Buffer-Related Current Slump in AlGaN/GaN HEMTs
K. Horio, Shibaura Institute of Technology, JP
5:55 A Circuit Compatible Analytical Device Model for Nanowire FET Considering Ballistic and Drift-Diffusion Transport
B.C. Paul, R. Tu, S. Fujita, M. Okajima, T. Lee and Y. Nishi, Toshiba America Research, US
6:00 Numerical Modeling for Comparison of Emitter-Base Designs of InGaP/GaAs Heterojunction Bipolar Transistors
J.M. Lopez-Gonzalez, Universitat Politecnica de Catalunya, ES

Thursday May 24

Back to Top
8:00 WCM: Special OverviewGrand Ballroom A
 Session chair: Colin McAndrew, Freescale Semiconductor, USA
8:00 Monolithic Concept and the Inventions of Integrated Circuits by Kilby and Noyce
A.N. Saxena, Rensselaer International Science Company, US
Back to Top
8:30 WCM: Interconnect/parasitic/process modelsGrand Ballroom A
 Session chair: Jamal Deen, McMaster University, Canada
8:30 RCL Modeling and characterization of X Architecture Diagonal lines for Sub-100nm SoC design
N. Arora, Cadence Design System, Inc., US (invited)
9:00 Modeling the Geometry-Dependent Parasitics in Multi-Fin FinFETs
M. Chan and W. Wu, HKUST, HK (invited)
9:30 Analysis of Halo Implanted MOSFETs.
C.C. McAndrew and P.G. Drennan, Freescale Semiconductor, US (invited)
Back to Top
10:30 WCM: FET/HBT modelsGrand Ballroom A
 Session chair: Narain Arora, Cadence Design Systems, USA
10:30 Modeling the electrical characteristics of FET-type sensors for biomedical applications
M.J. Deen and M.W. Shinwari, McMaster University, CA (invited)
11:00 Non-standard geometry scaling effects
M. Schröter and S. Lehmann, Technische Universität Dresden, DE (invited)
11:30 Theory of source-drain partitioning in MOSFET
A.S. Roy, C.C. Enz and J.M Sallese, EPFL, CH
11:50 Gummel Symmetry with Higher-order Derivatives in MOSFET Compact Models
G.H. See, X. Zhou, K. Chandrasekaran, S.B. Chiah, Z.M. Zhu, G.H. Lim, C.Q. Wei, S.H. Lin and G.J. Zhu, Nanyang Technological University, SG


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