Nano Science and Technology InstituteNano Science and Technology Institute
Nano Science and Technology Institute 2005 NSTI Nanotechnology Conference & Trade Show
Nanotech 2005
Bio Nano 2005
Business & Investment
Nano Impact Workshop
Index of Authors
Index of Keywords
Keynote Presentations
Confirmed Speakers
Participating Companies
Industry Focus Sessions
Nanotech Expo
Special Symposia
Venue 2005
Press Room
Site Map
Nanotech 2005 At A Glance
Nanotech Proceedings
Nanotechnology Proceedings
Global Partner
nano tech
Supporting Organizations
Nanotech 2005 Supporting Organization
Media Sponsors
Nanotech 2005 Medias Sponsors
Event Contact
696 San Ramon Valley Blvd., Ste. 423
Danville, CA 94526
Ph: (925) 353-5004
Fx: (925) 886-8461

Novel Nonvolatile Logic Circuits with Three-Dimensionally Stacked Nanoscale Memory Device

K. Abe, S. Fujita and T.H. Lee
Toshiba Corporation, JP

emerging memory, 3D stacking, nonvolatile logic circuit

Various emerging memories have been proposed for ultra high-density memory, such as phase change memory, organic memory or resistive memory. However, the potential of the emerging memories is not limited to RAM only. We have proposed that, by 3D stacking emerging memory on CMOS, logic circuits can be embedded in local interconnect, thereby enabling small area and low power consumption. D-type flip flop (D-F/F) is most frequently used as sequential logic circuits. We propose the nonvolatile D-F/F using emerging memory. The nonvolatile D-F/F consists of 3D stacked emerging memory and reference resistance connected in series with slave side cross-coupled inverters. Since the data is stored in emerging memory, supply voltage can be shut down to the unused logic block. To recall the stored data, the node voltage of output is determined by the RC delay depending on the resistance of emerging memory and reference. We demonstrate the recall operation by SPICE simulation. As a result the most feasible emerging memory is the resistive memory. By using these memories, small logic circuits with low power consumption can be realized. Such novel circuit design is much effective especially for FPGA consisting of a lot of D-type flip flops.

Back to Program

Sessions Sunday Monday Tuesday Wednesday Thursday Authors

Nanotech 2005 Conference Program Abstract

Gold Sponsors
Nanotech Gold Sponsors
Silver Sponsors
Nanotech Silver Sponsors
Gold Key Sponsors
Nanotech Gold Key Sponsors
Nanotech Ventures Sponsors
Nanotech Ventures Sponsors
Nanotech Sponsors
News Headlines
NSTI Online Community

© Nano Science and Technology Institute, all rights reserved.
Terms of use | Privacy policy | Contact