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Statistical Simulations of Oxide Leakage Current in MOS Transistor and Floating Gate Memories

L. Larcher and P. Pavan
Università di Modena e Reggio Emilia, IT

flash memories, semiconductor device reliability, modeling, oxide reliability, SILC

The purpose of this paper is to illustrate a physically-based model allowing the statistical simulations of oxide leakage currents in MOS transistors and Floating Gate memories. This model computes the leakage current through defects randomly generated in the oxide, in case accounting for the formation of percolation paths. Furthermore, a calculation procedure has been developed to calculate the threshold voltage of FG memories from the simulated oxide leakage current in some reliability conditions, thus allowing to investigate their actual Flash data retention issues and their future trends. To this regards, it will be shown how this simulation model can be used to investigate threshold voltage shift occurring in retention conditions in FG memories after both Program/Erase cycles, i.e. electrical stress and radiation exposure.

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