Authors: G. Gutierrez-Heredia, I. Mejia, M.E. Rivas-Aguilar, F.S. Aguirre-Tostado, M.A. Quevedo-Lopez
Affilation: The University of Texas at Dallas, United States
Pages: 103 - 106
Keywords: inverter, ZnO, TFT
We report the development of low power ZnO-based inverters. Inverters were evaluated as function of gate dielectric thicknesses and electrically characterized at several power supply voltages. The logic inverters gain increases one order of magnitude when increasing the power supply voltage. Inverter fabrication was carried out using standard photolithography at temperatures below 100 ˚C. Atomic layer deposited (ALD) hafnium oxide (HfO2) was used as the gate dielectric. HfO2 thicknesses ranged from 15 to 90 nm .The ZnO active layers were deposited by pulsed laser deposition (PLD). We shows the average mobility (µ), threshold voltage (VTH) and VTH-shift extracted from TFTs with different dielectric thicknesses. Calculated inverter gains were 23, 30 and 112 for the different dielectric thickness. Higher TFT mobilities and logic inverter gains can be achieved increasing the applied voltage, yet the dielectric has to be thicker to manage larger voltages. Also thicker gate dielectric will lead to more traps at the dielectric/semiconductor interface and therefore larger operation voltage shifts for the devices.