Authors: M. Szermer, L. Kotynia, P. Pietrzak, M. Janicki, A. Napieralski
Affilation: Technical University of Lodz, Poland
Pages: 562 - 565
Keywords: many-core architecture, thermal coupling, ASIC
The main goal of the paper is to present the design of an ASIC dedicated to thermal analysis of many-core architectures. Due to the fact that the process of designing real multi-core microprocessors is expensive and time consuming, the authors decided to design a special test ASIC which will be used (together with a dedicated simulator) to estimate thermal dependencies between cores in many-core processors. The presented ASIC consists of 384 heat cells which represent the power dissipation sources in real many-core microprocessors. These heat cells create a 10x24 array. The presented ASIC is a part of a project aimed at defining the thermal coupling coefficients between cores in many-core architectures using a dedicated thermal-logic simulator. The proposed ASIC will be used for empirical verification of this method. The full paper will present in detail the architecture and the simulation results of this ASIC.