Nano Science and Technology Institute
Nanotech 2012 Vol. 2
Nanotech 2012 Vol. 2
Nanotechnology 2012: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational (Volume 2)
Chapter 10: Compact Modeling

Field-Based 3D Capacitance Modeling for sub-45-nm On-Chip Interconnect

Authors:A. Zhang, W. Zhao, Y. Ye, J. He, A. Chen, M. Chan
Affilation:Beijing University of Aeronautics and Astronautics, CN
Pages:804 - 808
Keywords:capacitance modeling, fringe capacitance, terminal capacitance, electric field, interconnect
Abstract:Considering both two-dimensional and three-dimensional single wire above plate, the proposed method decomposes the electric field into various regions and gives solutions for each part. The total ground capacitance is the summation of all components. The solution can be easily extended to the case of two parallel wires. Its physical base minimizes the complexity and error in a traditional model fitting process. The new compact model accurately predicts the capacitance value, compared to the COMSOL simulations, for not only the nominal wire dimensions from the latest ITRS updates, but also a wide range of other back-end-of-the-line dimensions.
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