Simulation of Field-Plate Effects on Surface-State-Related Lag and Current Slump in GaAs FETs

	Nanotech 2011 Vol. 2 Nanotechnology 2011: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational Chapter 9: Nano & Micro: Computational Methods, Simulation & Software Tools
	Simulation of Field-Plate Effects on Surface-State-Related Lag and Current Slump in GaAs FETs
Authors:	T. Tanaka, K. Itagaki, A. Nakajima, K. Horio
Affilation:	Shibaura Institute of Technology, JP
Pages:	595 - 598
Keywords:	GaAs FET, power slump, drain lag, gate lag, surface state
Abstract:	In this study, we carry out two-dimensional transient analysis of field-plate GaAs MESFETs by taking surface states into account. Quasi-pulsed current-voltage curves are derived from the transient characteristics. We show that drain lag and current slump (power slump) due to surface states are reduced by introducing a field plate because the fixed potential at the field plate mitigates trapping effects of the surface states. The dependence of lag and current slump on the field-plate length and SiO2 passivation layer thickness is also studied. We show that it is possible to reduce the current slump and maintain the high-frequency performance of GaAs FETs at optimum values of the field-plate length and SiO2 layer thickness.
ISBN:	978-1-4398-7139-3
Pages:	854
Hardcopy:	$199.95

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