Nano Science and Technology Institute
Nanotech 2011 Vol. 2
Nanotech 2011 Vol. 2
Nanotechnology 2011: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational
Chapter 10: Compact Modeling

Modeling of High Voltage Devices for ESD Event Simulation

Authors:Y. Zhou, J. Salcedo, J.-J. Hajjar
Affilation:Analog Devices, Inc., US
Pages:747 - 750
Keywords:ESD, model, high voltage
Abstract:BCDMOS process technologies are key in enabling highly integrated mixed-signal application for the automotive, medical and industrial sectors. Achieving satisfactory ESD performance in high voltage mixed-signal applications requires synthesized co-design using circuit-level ESD event simulation with accurate compact models. However, ESD capable compact models for high voltage core devices and complex protection clamps are not readily available in the industry. Compared to the low voltage MOS devices, there are distinct properties in high voltage MOS devices that need to be addressed. A new ESD compact modeling using macro-modeling approach is introduced in this work for high voltage DMOS (Drain-extended MOS) devices and protection clamps to address the distinct device properties in high voltage devices and the requirements in ESD simulation for high voltage mixed-signal applications. The DMOS ESD model consists of sub-circuits that are built on top of the standard (MOS20) model. On the other hand, the high voltage clamp, which is a SCR (Silicon-Controlled-Rectifier)-type array, is modeled by incorporating advanced bipolar models. The simulation of these high voltage devices agrees well with the transient and quasi-static TLP measurements for multiple high voltage devices types when operated under different stress conditions.
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