Liao Y.-B., Chiang M-H, Kim K., Hsu W.-C.
National Cheng Kung University, TW
Keywords: gate-all-around (GAA), junctionless (JL), nanowire FETs, SRAM
3-D numerical simulation shows that both the conventional and JL nanowire FETs are sensitive to structural variation whereas the former is more tolerable. Due to more increased Ion/Ioff for lower D and WSi in JL, the proposed SRAM cell can achieve higher RSNM for aggressive technology scaling at/beyond the 14 nm node. This study indicates that process-induced non-idea nanowire structure is not a showstopper in Si-nanowire technologies.
Journal: TechConnect Briefs
Volume: 2, Nanotechnology 2011: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational
Published: June 13, 2011
Pages: 46 - 49
Industry sector: Sensors, MEMS, Electronics
Topics: Nanoelectronics, Photonic Materials & Devices
ISBN: 978-1-4398-7139-3