Variability Study for Silicon Nanowire FETs

	Nanotech 2011 Vol. 2 Nanotechnology 2011: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational Chapter 1: Nano Electronics & Photonics
	Variability Study for Silicon Nanowire FETs
Authors:	Y.-B. Liao, M.-H. Chiang, K. Kim, W.-C. Hsu
Affilation:	National Cheng Kung University, TW
Pages:	46 - 49
Keywords:	nanowire FETs, gate-all-around (GAA), junctionless (JL), SRAM
Abstract:	3-D numerical simulation shows that both the conventional and JL nanowire FETs are sensitive to structural variation whereas the former is more tolerable. Due to more increased Ion/Ioff for lower D and WSi in JL, the proposed SRAM cell can achieve higher RSNM for aggressive technology scaling at/beyond the 14 nm node. This study indicates that process-induced non-idea nanowire structure is not a showstopper in Si-nanowire technologies.
ISBN:	978-1-4398-7139-3
Pages:	854
Hardcopy:	$199.95

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