Authors: Y.-B. Liao, M.-H. Chiang, K. Kim, W.-C. Hsu
Affilation: National Cheng Kung University, Taiwan
Pages: 46 - 49
Keywords: nanowire FETs, gate-all-around (GAA), junctionless (JL), SRAM
3-D numerical simulation shows that both the conventional and JL nanowire FETs are sensitive to structural variation whereas the former is more tolerable. Due to more increased Ion/Ioff for lower D and WSi in JL, the proposed SRAM cell can achieve higher RSNM for aggressive technology scaling at/beyond the 14 nm node. This study indicates that process-induced non-idea nanowire structure is not a showstopper in Si-nanowire technologies.