Nanotech 2010 Vol. 2
Nanotech 2010 Vol. 2
Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational

Compact Modeling Chapter 11

Source/Drain Edge Modeling for DG MOSFET Compact Model

Authors: T. Nakagawa, S. O’uchi, T. Sekigawa, T. Tsutsumi, M. Hioki, H. Koike

Affilation: AIST (National Institute of Advanced Industrial Science and Technology), Japan

Pages: 781 - 784

Keywords: compact model, MOSFET, double-gate

Abstract:
A compact model for four terminal double-gate MOSFET, based on double charge-sheet approximation with carrier velocity saturation, is discussed. Although it is a monolithic model both for conductance and intrinsic capacitances, it is not a complete analytical model along the entire channel, since space charge regions at the source/drain edge have not been modeled. In this report, we propose the modeling of these regions, and discuss its effect on the length of the effective gate length, and on the conductance modulation caused by the gate underlap. If source/drain doping profile is assumed to be sufficiently abrupt, this region provides small correction to the effective gate length. The region becomes significant when relatively long underlap between the source and the gate exists, causing significant current decrease. When the underlap is at drain side, current decrease occurs only when the drain voltage is small. Mobility models with carrier velocity saturation predict very low mobility in this region although carrier distribution in the phase space is almost in equilibrium everywhere. It was found, by ATLAS simulation, that the voltage drop across this region was sensitive to the mobility model.


ISBN: 978-1-4398-3402-2
Pages: 862
Hardcopy: $189.95

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