Nanotech 2010 Vol. 2
Nanotech 2010 Vol. 2
Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational

Electronics & Photonics Chapter 1

3-state Quantum Dot Gate FETs in Designing High Sampling Rate ADCs

Authors: S. Karmakar, J.A. Chandy, F.C. Jain

Affilation: University of Connecticut, United States

Pages: 17 - 20

Keywords: ADC, QDFETs, quantum dots, 3-state devices, comparators

Abstract:
In this work we present Cadence simulation of 3-bit Analog-to-Digital Converters (ADCs) based on compact 3-QDFET comparators, using 32nm design rules with BSIM 3.2.0 and BSIM 3.2.4 models [3]. In addition, we present the precise control of the threshold voltage of variable threshold voltage transistor which will remove R-2R ladder problem in conventional analog-to-digital converters(ADCs).

3-state Quantum Dot Gate FETs in Designing High Sampling Rate ADCs

ISBN: 978-1-4398-3402-2
Pages: 862
Hardcopy: $189.95