A Fan-in Bounded Low Delay Adder for Nanotechnology

	Nanotech 2010 Vol. 2 Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational Chapter 1: Electronics & Photonics
	A Fan-in Bounded Low Delay Adder for Nanotechnology
Authors:	Y. Sun, M.D. Wagh
Affilation:	Lehigh University, US
Pages:	83 - 86
Keywords:	nanoelectronics, adder, threshold logic
Abstract:	This paper presents an adder designed specifically for nanoelectronics. It exploits the basic characteristics of nanoelectronic technologies such as the RTD, SET and QCA to provide an adder that has a very low delay and a bounded fan-in. It is known that a low fan-in bound implies high reliability. This adder, for the first time allows user a trade-off between the fan-in bound, the complexity and the speed. A comparison with other adders available in the literature has been provided. Design of an 8-bit adder built with resonant tunneling diodes (RTD) based on these principles is presented.
ISBN:	978-1-4398-3402-2
Pages:	862
Hardcopy:	$189.95

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