Nanotech 2009 Vol. 3
Nanotech 2009 Vol. 3
Nanotechnology 2009: Biofuels, Renewable Energy, Coatings, Fluidics and Compact Modeling

Workshop on Compact Modeling Chapter 9

Compact Modeling of Dynamic Threshold Voltage of FinFET High K Gate Stack and Application in Circuit Simulation

Authors: F. He, C. Ma, B. Li, L. Zhang, X. Zhang, X. Lin

Affilation: SZPKU, China

Pages: 596 - 599

Keywords: FinFET, dynamic threshold voltage, device physics, compact modeling

Abstract:
Compact modeling study of dynamic threshold voltage of FinFET high K gate stack is proposed in this paper. Both slow transient (STCE) and fast transient charging effect (FTCE) are included in this model. Finally, this model is applied in FinFET reliability and circuit performances are simulated. The result shows that, the drain circuit (Id) degradation in FinFET is much more obvious than normal MOSFETs with the same processes and the variation of Id is slower in higher temperature. However, the dynamic threshold voltage in high K stack seems not affect the delay time of reverser simulated by HSPICE.

Compact Modeling of Dynamic Threshold Voltage of FinFET High K Gate Stack and Application in Circuit Simulation

ISBN: 978-1-4398-1784-1
Pages: 694
Hardcopy: $179.95