Authors: R. Kaur, R. Chaujar, M. Saxena, R.S. Gupta
Affilation: University of Delhi, India
Pages: 814 - 817
Keywords: NUDC, voltage doping transformation, ATLAS
Since past three decades, in the pursuit of superior performances relative to high-speed circuits and packing density, miniaturization of device dimensions has been adopted as a powerful tool. Gradually, as device feature sizes move into sub-100nm regime, the device characteristics degrade due to the emergence of typical SCEs. To combat these SCEs, the design of ultra-small devices necessitates the use of various channel engineered architectures using Non-Uniform Doping Channel (NUDC) profiles. In this paper, an efficient drain current model for sub-100nm channel engineered LDD, halo and their combination, has been presented. Using Poisson’s equation, a simple 2D potential distribution model in the channel for NUDC MOSFETs has been developed using which the drain current model is obtained. The model incorporates DIBL effect using Voltage Doping Transformation (VDT) method, which replaces the influence of the lateral drain-source field by an equivalent reduction in the channel doping concentration. Comparisons have been drawn among the studied devices based on their improved subthreshold and on-state performances.