Nanotech 2008 Vol. 3
Nanotech 2008 Vol. 3
Nanotechnology 2008: Microsystems, Photonics, Sensors, Fluidics, Modeling, and Simulation - Technical Proceedings of the 2008 NSTI Nanotechnology Conference and Trade Show, Volume 3

Compact Modeling Chapter 7

Capacitance modeling of Short-Channel DG and GAA MOSFETs
H. Børli, S. Kolberg, T.A. Fjeldly
Norwegian University of Science and Technology, NO

New Properties and New Challenges in MOS Compact Modeling
X. Zhou, G.H. See, G. Zhu, Z. Zhu, S. Lin, C. Wei, A. Srinivas, J. Zhang
Nanyang Technological University, SG

Unified Regional Surface Potential for Modeling Common-Gate Symmetric/Asymmetric Double-Gate MOSFETs with Quantum-Mechanical Effects
G.H. See, X. Zhou, G. Zhu, Z. Zhu, S. Lin, C. Wei, J. Zhang, A. Srinivas
Nanyang Technological University, SG

Quasi-2D Surface-Potential Solution to Three-Terminal Undoped Symmetric Double-Gate Schottky-Barrier MOSFETs
G. Zhu, G.H. See, X. Zhou, Z. Zhu, S. Lin, C. Wei, J. Zhang, A. Srinivas
Nanyang Technological University, SG

Construction of a Compact Modeling Platform and Its Application to the Development of Multi-Gate MOSFET Models for Circuit Simulation
M. Miura-Mattausch, M. Chan, J. He, H. Koike, H.J. Mattausch, T. Nakagawa, Y.J. Park, T. Tsutsumi, Z. Yu
Hiroshima University, JP

Unified Regional Surface Potential for Modeling Common-Gate Symmetric/Asymmetric Double-Gate MOSFETs with Any Body Doping
G.H. See, X. Zhou, G. Zhu, Z. Zhu, S. Lin, C. Wei, J. Zhang, A. Srinivas
Nanyang Technological University, SG

Surface Potential versus Voltage Equation from Accumulation to Strong Region for Undoped Symmetric Double-Gate MOSFETs and Its Continuous Solution
J. He, Y. Chen, B. Li, Y. Wei, M. Chan
PEKING University, CN

Modeling of Floating-Body Devices Based on Complete Potential Description
N. Sadachika, T. Murakami, M. Ando, K. Ishimura, K. Ohyama, M. Miyake, H.J. Mattausch, M. Miura-Mattausch
Hiroshima-University, JP

The Driftless Electromigration Theory (Diffusion-Generation-Recombination-Trapping)
C-T Sah, B.B. Jie
University of Florida, US

Adaptable Simulator-independent HiSIM2.4 Extractor
T. Gneiting, T. Eguchi, W. Grabinski
AdMOS GmbH Advanced Modeling Solutions, DE

Recent Advancements on ADMS Development
B. Gu, L. Lemaitre
Freescale Semiconductor, US

Source/Drain Junction Partition in MOS Snapback Modeling for ESD Simulation
Y. Zhou, J.-J. Hajjar
Analog Devices, Inc., US

Improved layout dependent modeling of the base resistance in advanced HBTs
S. Lehmann, M. Schroter
University of Technology Dresden, DE

The Bipolar Field-Effect Transistor Theory (A. Summary of Recent Progresses)
B.B. Jie, C-T Sah
Peking University, CN

The Bipolar Field-Effect Transistor Theory (B. Latest Advances)
C-T Sah, B.B. Jie
University of Florida, US

An Accurate and Versatile ED- and LD-MOS Model for High-Voltage CMOS IC Spice Simulation
B. Tudor, J.W. Wang, B.P. Hu, W. Liu, F. Lee
Synopsys, Inc., US

Compact Modeling of Noise in non-uniform channel MOSFET
A.S. Roy, C.C. Enz, T.C. Lim and F. Danneville
CSEM & EPFL, CH

An Iterative Approach to Characterize Various Advanced Non-Uniformly Doped Channel Profiles
R. Kaur, R. Chaujar, M. Saxena, R.S. Gupta
University of Delhi, IN

Modeling of Spatial Correlations in Process, Device, and Circuit Variations
N. Lu
IBM, US

Model Implementation for Accurate Variation Estimation of Analog Parameters in Advanced SOI Technologies
S. Suryagandh, N. Subba, V. Wason, P. Chiney, Z-Y Wu, B.Q. Chen, S. Krishnan, M. Rathor, A. Icel
Advanced Micro Devices, US

Modeling of gain in advanced CMOS technologies
A. Spessot, F. Gattel, P. Fantini, A. Marmiroli
STMicroelectronics, IT

Effective Drive Current in CMOS Inverters for Sub-45nm Technologies
J. Hu, J.E. Park, G. Freeman, H.S.P. Wong
Stanford University, US

Process Aware Compact Model Parameter Extraction for 45 nm Process
A.P. Karmarkar, V.K. Dasarapu, A.R. Saha, G. Braun, S. Krishnamurthy, X.-W. Lin
Synopsys (India) Pvt. Ltd., IN

Analytical Modelling and Performance Analysis of Double-Gate MOSFET-based Circuit Including Ballistic/quasi-ballistic Effects
S. Martinie
CEA LETI-MINATEC, FR

An Improved Impact Ionization Model for SOI Circuit Simulation
X. Xi, F. Li, B. Tudor, W. Wang, W. Liu, F. Lee, P. Wang, N. Subba, J-S Goo
Synopsys Inc, US

Parameter Extraction for Advanced MOSFET Model using Particle Swarm Optimization
R.A. Thakker, M.B. Patil, K.G. Anil
Indian Institute of Technology, IN

Compact Models for Double Gate MOSFET with Quantum Mechanical Effects using Lambert Function
H. Abebe, H. Morris, E. Cumberbatch, V. Tyree
University of Southern California, ISI, US

Neural Computational Approach for FinFET Modeling and Nano-Circuit Simulation
M.S. Alam, A. Kranti, G.A. Armstrong
Z. H. College of Engineering & Technology, IN

Closed Form Current and Conductance Model for Symmetric Double-Gate MOSFETs using Field-dependent Mobility and Body Doping
V. Hariharan, R. Thakker, M.B. Patil, J. Vasi, V.R. Rao
IIT Bombay, IN

Comparison of Four-terminal DG MOSFET Compact Model with Thin Si channel FinFET Devices
T. Nakagawa, T. Sekigawa, T. Tsutsumi, Y. Liu, M. Hioki, S. O’uchi, H. Koike
Electroinformatics Group, JP

MOSFET Compact Modeling Issues for Low Temperature (77 K - 200 K) Operation
P. Martin, M. Cavelier, R. Fascio, G. Ghibaudo
CEA-LETI Minatec, FR

Interface-trap Charges on Recombination DC Current-Voltage Characteristics in MOS transistors
Z. Chen, B.B. Jie, C-T Sah
Nanyang Technological University, SG

Compact Analytical Threshold Voltage Model for Nanoscale Multi-Layered-Gate Electrode Workfunction Engineered Recessed Channel (MLGEWE-RC) MOSFET
R. Chaujar, R. Kaur, M. Saxena, M. Gupta, R.S. Gupta
University of Delhi, IN

Compact Model of the Ballistic Subthreshold Current in Independent Double-Gate MOSFETs
D. Munteanu, M. Moreau, J.L. Autran
L2MP-CNRS, FR

Physical Carrier Mobility in Compact Model of Independent Double Gate MOSFET
M. Reyboz, P. Martin, O. Rozeau, T. Poiroux
cea-leti, FR

A Technique for Constructing RTS Noise Model Based on Statistical Analysis
C-Q Wei, Y-Z Xiong, X. Zhou
Nanyang Technological University, SG

Impact of Non-Uniformly Doped and Multilayered Asymmetric Gate Stack Design on Device Characteristics of Surrounding Gate MOSFETs
H. Kaur, S. Kabra, S. Haldar, R.S. Gupta
University of Delhi, IN

HiSIM-HV: a complete surface-potential-based MOSFET model for High Voltage Applications
Y. Oritsuki, M. Yokomiti, T. Sakuda, N. Sadachika, M. Miyake, T. Kajiwara, U. Feldmann, H.J. Mattausch, M. Miura-Mattausch
Hiroshima-University, JP

Si-Based Process Aware SPICE Models for Statistical Circuit Analysis
S. Krishnamurthy, V.K. Dasarapu, Y. Mahotin, R. Ryles, F. Roger, S. Uppal, P. Mukherjee, A. Cuthbertson, X-W Lin
Synopsys Inc., US


ISBN: 978-1-4200-8505-1
Pages: 940
Hardcopy: $159.95